The invention relates to a memory cell arrangement for a static memory, realized in integrated circuit technology, which is provided with a number of control lines for writing, reading and retaining the memory information in the cell, which cell comprises two cross-coupled transistors which are connected to the control lines.
It is specifically the object of the invention to reduce the number of control lines of such a cell in order to save area on the semiconductor body on which the memory is integrated. Generally, two pairs of control lines per cell are required, namely two word lines and two bit lines, by means of which information can be written into, read out of or retained in such a cell. The German "Auslegeschrift" No. 2,147,833, in FIG. 8 et seq, reveals examples which employ only three control lines per cell, but in practice such memories are found not to perform satisfactorily, because during stand-by of such a cell a current flows through the bit lines (DL), so that in the case of a large number of cells a parasitic current may flow which is so large that incorrect information may be obtained when a selected cell is read.